MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 126

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
received BG through the arbitration process, and BGACK must be inactive, indicating that
no other bus master has claimed ownership of the bus.
Figure 4-34 is a flowchart showing the detail involved in bus arbitration for a single device.
This technique allows processing of bus requests during data transfer cycles.
The QUICC has a synchronous arbitration timing mode to reduce the BR to BG delay to one
clock in the idle bus case (see Figure 4-35). Figure 4-36 illustrates the active bus case.
BR is negated at the time that BGACK is asserted. This type of operation applies to a system
consisting of the QUICC and one device capable of bus mastership. In a system having a
number of devices capable of bus mastership, BR from each device can be wire-ORed to
the QUICC. In such a system, more than one bus request could be asserted simultaneously.
BG is negated a few clock cycles after the transition of BGACK. However, if bus requests
are still pending after the negation of BG, the QUICC asserts another BG within a few clock
cycles after it was negated. This additional assertion of BG allows external arbitration cir-
cuitry to select the next bus master before the current bus master has finished using the bus.
The following paragraphs provide additional information about the three steps in the arbitra-
tion process. Bus arbitration requests are recognized during normal processing, HALT
assertion, and when the CPU32+ has halted due to a double bus fault.
4-50
Figure 4-34. Bus Arbitration Flowchart for Single Request
1) ASSERT BG
1) NEGATE BG (AND WAIT FOR
BGACK TO BE NEGATED)
RE-ARBITRATE OR RESUME
TERMINATE ARBITRATION
GRANT BUS ARBITRATION
PROCESSOR OPERATION
QUICC
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
1) EXTERNAL ARBITRATION DETERMINES
2) NEXT BUS MASTER WAITS FOR BGACK
3) NEXT BUS MASTER ASSERTS BGACK
4) BUS MASTER NEGATES BR
1) PERFORM DATA TRANSFERS (READ AND
1) NEGATE BGACK
1) ASSERT BR
NEXT BUS MASTER
TO BE NEGATED
TO BECOME NEW MASTER
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES
ACKNOWLEDGE BUS MASTERSHIP
OPERATE AS BUS MASTER
RELEASE BUS MASTERSHIP
REQUESTING DEVICE
REQUEST THE BUS