MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 508

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Serial Communication Controllers (SCCs)
TC—Tx CRC
CM—Continuous Mode
The following status bits are written by the HDLC controller after it has finished transmitting
the associated data buffer.
UN—Underrun
CT—CTS Lost
Data Length
Tx Data Buffer Pointer
7.10.17.11 HDLC EVENT REGISTER (SCCE). The SCCE is called the HDLC event regis-
ter when the SCC is operating as an HDLC controller. It is a 16-bit register used to report
events recognized by the HDLC channel and to generate interrupts. On recognition of an
event, the HDLC controller will set the corresponding bit in the HDLC event register. Inter-
rupts generated by this register may be masked in the HDLC mask register. An example of
interrupts that may be generated in the HDLC protocol is shown in Figure 7-53.
7-184
This bit is valid only when the L-bit is set; otherwise, it is ignored.
The HDLC controller encountered a transmitter underrun condition while transmitting the
associated data buffer.
CTS in NMSI mode or layer 1 grant was lost in GCI mode during frame transmission. If
data from more than one buffer is currently in the FIFO when this error occurs, this bit will
be set in the Tx BD that is currently open.
The data length is the number of bytes the HDLC controller should transmit from this BD’s
data buffer. It is never modified by the CP. The value of this field should be greater than
zero.
The transmit buffer pointer, which contains the address of the associated data buffer, may
be even or odd. The buffer may reside in either internal or external memory. This value is
never modified by the CP.
0 = Transmit the closing flag after the last data byte. This setting can be used for test-
1 = Transmit the CRC sequence after the last data byte.
0 = Normal operation.
1 = The R-bit is not cleared by the CP after this BD is closed, allowing the associated
ing purposes to send a bad CRC after the data.
data buffer to be retransmitted automatically when the CP next accesses this BD.
However, the R-bit will be cleared if an error occurs during transmission, regard-
less of the CM bit.
Freescale Semiconductor, Inc.
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