MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 749

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The transparent mode register is implemented using the GSMR and the PSMR. One GSMR
and one PSMR exist for each SCC. The definition of the PSMR differs based on the protocol
used.
The data synchronization register (DSR) is also available on the QUICC. When used in
UART mode to generate fractional stop bits, the user should note that the encodings have
changed slightly.
The SCC event register (SCCE) is also available on the QUICC, but the register now has 10
bit positions to include new bit functions. The configuration of this register depends on the
protocol mode.
The SCC mask register (SCCM) is also available on the QUICC, but the register now has
10 bit positions to include new bit functions. The configuration of this register depends on
the protocol mode. Since the SCCM has the exact format as the SCCE, see the preceding
SCCE description for details.
The REVD bit is located in the GSMR.
The NTSYN bit becomes the TTX and TRX bits in the GSMR. On the QUICC the user can
independently enable the totally transparent protocol to work on the receiver or transmitter
while another protocol (such as HDLC) runs on the transmitter or receiver.
If the EXSYN bit was set, the CDP and CTSP bit in the GSMR should be set for compat-
ibility. The user may also wish to leave the CDS and CTSS bits cleared in the GSMR. The
user may wish to set the RSYN bit in the GSMR to remain compatible with the MC68302.
In UART mode, the RX, TX, BSY, CCR, BRK, and IDL bits exist unchanged. The CD and
CTS bits are no longer needed because the interrupt controller supports a separate vector
for each event.
In HDLC mode, the RXB, TXB, BSY, RXF, TXE, and IDL bits exist unchanged. The CD
and CTS bits are no longer needed because the interrupt controller supports a separate
vector for each event.
In BISYNC mode, the RX, TX, BSY, RCH, and TXE bits exist unchanged. The CD and
CTS bits are no longer needed because the interrupt controller supports a separate vector
for each event.
DDCMP is a microcode RAM product on the QUICC. The port of DDCMP from the
MC68302 is not discussed in this section.
V.110 is not supported on the QUICC.
In totally transparent mode, the RX, TX, BSY, RCH, and TXE bits exist unchanged. The
CD and CTS bits are no longer needed because the interrupt controller supports a sepa-
rate vector for each event.
The SYNL bits in the GSMR were added to offer more synchro-
nization options than are available on the MC68302. Additional-
ly, a CRC may be generated in transparent mode using the
TCRC bits.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Applications