MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 656

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Parallel Interface Port (PIP)
7.13.2 PIP Overview
The PIP is shown in Figure 7-84. The PIP may be operated as an 18-bit general-purpose I/
O port or in one of three handshake modes:
When in one of the handshake modes, the PIP is controlled either by the RISC controller or
the CPU32+ core. When the PIP is under RISC control, data is prepared by the CPU32+
core (or other host processor) using the same general BD structures as are used for the
SCCs. Thus, the PIP can transfer or receive blocks of characters without interrupting the
host processor. The data block may span several linked buffers; therefore, an entire block
may be received or transmitted without intervention from the CPU32+ core. When the PIP
is under CPU32+ core control (or the control of an external processor), the PIP is controlled
directly by the core one byte/word at a time.
When the interlocked or pulsed handshake modes are used, the PIP offers programmable
timing attributes such as setup time, pulse width, etc. The interlocked handshake mode sup-
ports level-sensitive handshake control signals. The pulsed handshake mode supports
edge-sensitive handshakes like those used for the Centronics interface.
The PIP mode of operation may be configured independently for two groups of port B pins:
PB7–PB0 and PB17–PB8. This configuration allows an 8-bit PIP data port to be defined,
rather than a full 16-bit data port.
7-332
• 8- or 16-Bit Strobed I/O Port with Two Interlocked Handshake Signals
• 8- or 16-Bit Strobed I/O Port with Two Pulsed Handshake Signals
• 8- or 16-Bit Transparent I/O Port with No Handshake Signals
PERIPHERAL BUS
DATA REGISTER
PORT B PINS
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 7-84. PIP Block Diagram
MC68360 USER’S MANUAL
HANDSHAKE
CONTROL
Go to: www.freescale.com
IMB
PORT B OPEN DRAIN REGISTER
PIP CONFIGURATION REGISTER
TIMING PARAMETER REGISTER
PORT B PIN ASSIGNMENTS
PORT B DATA DIRECTION
PIP EVENT REGISTER
PIP MASK REGISTER
PTPR
PBDIR
PBPAR
PIPE
PIPC
PBODR
PIPM