MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 923

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
APPENDIX C
RISC MICROCODE FROM RAM
The RISC processor in the QUICC has an option to execute microcode from the first 512 or
1024 bytes of the internal dual-port RAM. Motorola uses this feature to enhance existing pro-
tocols or implement additional protocols. Customers can purchase one or more of these
RAM microcodes in an object-code format and download it to the QUICC dual-port RAM dur-
ing system initialization.
The RAM microcode is provided by Motorola as a set of S-records that can be downloaded
directly to an application development system or stored in a system EPROM. After system
reset, the binary of the microcode should be copied to the QUICC dual-port RAM. The
QUICC registers, including the RISC controller configuration register (RCCR), should be ini-
tialized as specified in the microcode RAM documentation. Before the RISC is used in the
system, the user should issue a reset command to the communications processor command
register (CR). The microcode RAM functions are available in addition to all protocols avail-
able in the standard QUICC microcode ROM.
The following microcode RAM protocols are completed, in progress, or under consideration
by Motorola. Please contact the local Motorola semiconductor sales office for further infor-
mation on these packages.
C.1 SIGNALING SYSTEM #7 CONTROLLER
Signalling System #7 (SS7) is a management protocol used in public switching networks.
The physical, data link, and network layer functions of the SS7 protocol are called the Mes-
sage Transfer Part (MTP).
The data link layer portion of the MTP (layer 2) is based upon HDLC frame formats. How-
ever, SS7 at layer 2 also includes some unique functions that are difficult to implement using
an unaltered HDLC controller. These functions include: counting the number of octets by
which a frame is too long; sending fill in signal units (FISUs) and link status signal units
(LSSUs) continuously; maintaining the SU Error Monitor; and filtering duplicate back-to-
back frames.
FISUs are 5 byte frames (three bytes plus 2 CRC bytes) that are sent continuously back-to-
back when no other data needs to be transmitted. LSSUs are also sent back-to-back during
the initial alignment of the protocol. LSSUs are 6 or 7 bytes long. SS7 also differs from
other HDLC-based protocols in that the closing flag of one frame can be the opening flag of
the next frame. Since these characteristics can make SS7 implementations very demand-
ing, the SS7 controller on the QUICC provides additional help in these areas.
MC68360 USER’S MANUAL
For More Information On This Product,
Go to: www.freescale.com