MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 713

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Num
Bit
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
0
1
2
3
4
5
6
7
8
9
Output
Output
Output
Output
Output
Output
Type
IO.ctl
IO.ctl
IO.ctl
IO.ctl
IO.ctl
IO.ctl
IO.ctl
IO.ctl
IO.ctl
IO.ctl
Cell
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin/Cell
Dsack1
Dsack0
g10.ctl
Name
reseth
Bgack
Ipipe1
pipe0I
freeze
Ifetch
g1.ctl
g2.ctl
g3.ctl
g4.ctl
g5.ctl
g6.ctl
Prty0
Prty1
g7.ctl
Prty2
Prty3
g8.ctl
g9.ctl
Cas0
Cas1
Cas2
Cas3
bclro
Bkpt
Irq6
Irq4
nc1
nc2
nc3
R/w
Bg
Ds
oe
As
Br
Freescale Semiconductor, Inc.
Table 8-2. Boundary Scan Bit Definition
For More Information On This Product,
Output
Output
Output
Output
Output
Output
Type
TS-O
TS-O
TS-O
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
—
—
—
$
MC68360 USER’S MANUAL
Go to: www.freescale.com
CTLCell
Output
g10.ctl
g10.ctl
g1.ctl
g1.ctl
g1.ctl
g1.ctl
g2.ctl
g3.ctl
g4.ctl
g4.ctl
g5.ctl
g5.ctl
g5.ctl
g5.ctl
g6.ctl
g7.ctl
g7.ctl
g7.ctl
g7.ctl
g8.ctl
g8.ctl
g9.ctl
g9.ctl
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Num
Bit
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
Output
Output
Output
Output
Output
Output
Output
Output
Type
IO.ctl
Input
Input
Cell
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Scan Chain Test Access Port
Pin/Cell
add.ctl
Add10
Add11
Add12
Add13
Add14
Add15
Add16
Add17
Add18
Add19
Add20
Add21
Add22
Add23
Add24
Add25
Add26
Add27
Name
Add0
Add1
Add2
Add3
Add4
Add5
Add6
Add7
Add8
Add9
Cs0
Cs1
Cs2
Cs3
Cs4
Cs5
Cs6
Cs7
Irq7
Tris
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
Input
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
CTLCell
Output
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
add.ctl
—
—
—
—
—
—
—
—
—
—
—