MC68EN360CAI25L Freescale Semiconductor, MC68EN360CAI25L Datasheet - Page 83

• Manufacturer Part Number: MC68EN360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MC68000r

Specifications of MC68EN360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• No. Of Pins: 240
• Supply Voltage Range: 4.75V To 5.25V
• Rohs Compliant: Yes
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

the port width. For instance, a 32-bit device always returns DSACKx for a 32-bit port (regard-
less of whether the bus cycle is a byte, word, or long-word operation).
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a
particular port size be fixed. A 32-bit port must reside on data bus bits 0–31, a 16-bit port
must reside on data bus bits 16–32, and an 8-bit port must reside on data bus bits 24–31.
This requirement minimizes the number of bus cycles needed to transfer data to 8- and 16-
bit ports and ensures that the QUICC correctly transfers valid data. The QUICC always
attempts to transfer the maximum amount of data on all bus cycles; for a long-word opera-
tion, it always assumes that the port is 32 bit wide when beginning the bus cycle.
The bytes of operands are designated as shown in Figure 4-2. The most significant byte of
a long-word operand is OP0, and OP3 is the least significant byte. The two bytes of a word-
length operand are OP2 (most significant) and OP3. The single byte of a byte-length oper-
and is OP3. These designations are used in the figures and descriptions that follow.
Figure 4-3 shows the required organization of data ports on the QUICC bus for 8, 16, and
32-bit devices. The four bytes shown are connected through the internal data bus and data
multiplexer to the external data bus. This path is the means through which the QUICC sup-
ports dynamic bus sizing and operand misalignment. Refer to 4.2.2 Misaligned Operands
for the definition of misaligned operand. The data multiplexer establishes the necessary
connections for different combinations of address and data sizes.
The multiplexer takes the four bytes of the 32-bit bus and routes them to their required posi-
tions. For example, OP0 can be routed to D24–D31, as would be the normal case, or it can
be routed to any other byte position to support a misaligned transfer. The same is true for
any of the operand bytes. The positioning of bytes is determined by the size and address
outputs.
LONG-WORD OPERAND
Figure 4-2. Internal Operand Representation
Freescale Semiconductor, Inc.
For More Information On This Product,
31
0P0
MC68360 USER’S MANUAL
Go to: www.freescale.com
WORD OPERAND
0P1
15
BYTE OPERAND
0P2
0P2
7
0P3
0P3
0P3
Bus Operation
0
0
0