TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 83

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

P7CR
(001EH)
P7FC
(001FH)
P7DR
(0087H)
P7
(001CH)
Bit symbol
Read/Write
Reset State
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Order Register
(1)
(2)
(3)
Note 1: Read-modify-write is prohibited for P7CR and P7FC.
Note 2: It is set to “Port” or “
Note 3: When NDRE and NDWE are used, set registers in the following order to avoid outputting a negative glitch.
P7
P7FC
P7CR
<P76F>
<P72F>
P76 Setting
P72 Setting
7
7
7
7
<P72C>
<P76C>
0
1
0
1
Bit2
0
1
1
0: Input port,
1:Output port
WAIT
Refer to following table
(Output latch register is
Data from external port
P76C
P76D
P76F
P76
(Reserved)
WAIT
RD
Input port
Input port
6
6
6
6
0
0
1
Bit1
0
1
1
Figure 3.5.15 Register for Port 7
set to “1”)
” by AM pin setting.
0
0
input
W
0: Input port,
NDR/
1:Output port,
R/ W
Port 7 Function register
Port 7 Control register
Port 7 Drive register
P75C
P75D
P75F
P75
B
(at <P72> = 0)
(at <P72> = 1)
5
5
5
0
5
1
NDWE
WRLH
Port 7 register
0
92CH21-81
Output port
Output port
(Reserved)
Input/Output buffer drive register for standby mode
output
1
1
output
0: port
1: EA25
P74F
P94D
P74
4
4
4
4
0
0
1
<P71F>
<P75F>
P71 Setting
P75 Setting
0: port
1: EA24
<P71C>
<P75C>
P73F
P73D
0
1
R/W
R/W
0
1
P73
W
3
3
3
3
0
0
1
NDR/ B input
(Reserved)
Refer to following table
(Output latch register is
Refer to following table
Data from external port
Input port
Input port
P72D
P72C
P72F
P72
2
2
2
0
2
0
1
0
0
set to “1”)
W
at (<P71> = 0)
(at <P71> = 1)
NDRE
WRLL
P71C
P71F
P71D
Output port
R/
Output port
P71
1
1
1
1
0
1
0
W
output
1
output
1
output
TMP92CH21
2009-06-19
0: port
1:
0/1 Note 2
P70F
RD
P70D
P70
0
0
0
1
0
1