TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 361

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.14.4
3.14.4.1 Description of Operation
3.14.4.2 Memory Space
3.14.4.3 Mapping of Display Memory and Panning Function
3.14.4.4 Data Transmission
TFT Color Display Mode
LCD size to control registers before setting start register.
reads data from source memory. After data reading from source data is completed, the
LCDC cancels the bus release request and the CPU will restart. The LCDC then
transmits LCD size data to the external LCD driver through the LD bus (the special
data bus only for LCD driver). At this time, the control signals (LCP0 etc.) connected
to the LCD driver output the specified waveform which is synchronized with the data
transmission.
data read from source memory (during DMA operation).
LCDSCC. LCDSCC is the base clock for the LCD controller, which is generated by
system clock f
special data bus and LCP0, LFR, LLP and LDIV.
to SR mode section.
input width can be selected. 8-bit and 12-bit widths are supported.
This is basically the same setting as for SR mode.
Set the mode of operation, start address of source data save memory, color level and
After setting start register, the LCDC outputs a bus release request to the CPU and
In TFT mode LCDC, the CPU is stopped by the internal BUSREQ signal during
The LCD controller generates control signals (LFR, LBCD, LLP etc.) from base clock
For TFT source driver, the following signals are supported: 8-bit RGB or 4-bit × RGB
And for TFT gate driver control, LCP1, LBCD and LGOE2 to LGOE0.
Memory space setting is the same as for SR mode. Refer to SR mode section.
Panning function and display memory mapping are the same as for SR mode. Refer
This LSI outputs display data form special bus for LCD driver. The LCD driver
SYS
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92CH21-359
TMP92CH21
2009-06-19