TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 308

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

ADMOD1
(12B9H)
ADMOD2
(12BAH)
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset
State
Function
Note: As pin AN3 also functions as the
ADTRG
VREF
application
control
0: Off
1: On
VREFON
R/W
with < ADTRGE > set to “1”.
7
0
7
Figure 3.11.3 AD Converter Related Register
IDLE2
0: Stop
1: Operate
I2AD
R/W
6
0
6
AD Mode Control Register 1
AD Mode Control Register 2
Always
write “0”
Always
write “0”
ADTRG
<ADCH1:0>
92CH21-306
5
0
−
5
−
0
11 (Note)
input pin, do not set < ADCH1:0 > = “11” when using
00
01
10
Always
write “0”
Always
write “0”
<SCAN>
4
−
0
4
−
0
Before starting conversion (before writing 1 to
ADMOD0<ADS>), set the <VREFON> bit to 1.
Analog input channel selection
IDLE2 control
Control of application of reference voltage to AD
converter
AD conversion start control by external trigger
(
0
1
0
1
0
1
Always
write “0”
ADTRG
Always
write “0”
Channel
fixed
AN0
AN1
AN2
AN3
Stopped
In operation
Off
On
Disabled
Enabled
0
3
−
0
3
−
0
input)
R/W
R/W
AN0
AN0→AN1
AN0→AN1→AN2
AN0→AN1→AN2→AN3
Always
write “0”
Always
write “0”
2
−
0
2
−
0
scanned
Channel
Analog input channel
selection
Always
write “0”
ADCH1
1
1
0
1
−
0
TMP92CH21
2009-06-19
AD external
trigger start
control
0: Disable
1: Enable
ADTRGE
ADCH0
0
0
0
0