TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 336

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

LCDCTL1
(0286H)
LCDSCC
(0287H)
LCDSIZE
(0284H)
LCDCTL0
(0285H)
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Note 1: Maximum size in color mode (STN,TFT) is 320 × 320.
Note 2: This LSI does not support 240-segment size, but if a cascade type segment driver is selected, it can used
1 bpp (Monochrome):
2 bpp (4 grayscales):
4 bpp (16 grayscales): 256 × 128
8 bpp (256 colors):
12 bpp (4096 colors):
When internal SRAM is set as display RAM, the maximum size is as below.
by setting for 256-segment size. In this case, a 256-segment display area must be prepared.
Common setting
0000: Reserved
0001: 64
0010: 120
0011: 128
0100: 160
LCP0 phase
0: Rise
1: Fall
LCP0P
COM3
R/W
R/W
SCC7
7
7
7
1
0
0
7
LCP1 phase
0: Rise
1: Fall
Column
data setting
0: Normal
1: All display
LCP1P
data “0”
COM2
LCDC Source Clock Counter Register
ALL0
R/W
R/W
R/W
SCC6
6
6
6
0
0
0
0
6
0101: 200
0110: 240
0111: 320
1000: 480
Others: Reserved
640 × 200
320 × 200
128 × 128
128 × 64
LCD Size Setting Register
LCD Control-0 Register
LCD Control-1 Register
LBCD phase
0: Low
1: High
Frame
divide
setting
0: Disable
1: Enable
FRMON
LBCDP
enable
enable
COM1
R/W
R/W
R/W
SCC5
92CH21-334
5
5
5
1
0
0
0
5
LCDC source clock counter bit7 to bit0
Always
write “0”.
COM0
R/W
R/W
SCC4
4
4
4
−
0
0
0
4
R/W
Segment setting
0000: Reserved 0101: 320
0001: 64
0010: 128
0011: 160
0100: 256
f
bit9
FP
SEG3
R/W
FP9
setting
R/W
SCC3
3
3
3
0
0
0
3
Built-in RAM
LCD driver
setting
0: Sequential
1: Random
MMULCD
access
access
SEG2
0110: 480
0111: 640
1000: 768
1001: 960
R/W
R/W
SCC2
2
2
2
0
0
0
2
LBCD width control
00 : LCP1_1CLK
01 : LCP1_2CLK
10 : LCP1_3CLK
11 : Reserved
f
bit8
FP
LBCDW1
SEG1
FP8
R/W
R/W
SCC1
R/W
setting
1
1
1
0
0
0
0
Others: Reserved
1
TMP92CH21
2009-06-19
LCDC start
0: Stop
1: Start
LBCDW0
START
SEG0
R/W
R/W
SCC0
R/W
0
0
0
0
0
0
0
0