TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 387

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TMP92xy21FG

Manufacturer Part Number
TMP92xy21FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy21FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
16
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
82
Power Supply Voltage(v)
3.0 to 3.6
SDUUDQM
SDULDQM
SDLUDQM
SDLLDQM
SDRAS
SDCAS
SDWE
SDCS
D31 to D0
A15 to A0
SDCKE
SDCLK
A10
(Structure of Data Bus: 32 bits × 1, operand Size: 4 bytes, address: 4 n + 0)
SDUUDQM
SDULDQM
SDLUDQM
SDLLDQM
D31 to D0
SDRAS
SDCAS
A15 to A0
SDWE
SDCS
SDCKE
SDCLK
A10
Bank active
RA
RA
Figure 3.16.2 Timing of Burst Read Cycle
Figure 3.16.3 Timing of CPU Write Cycle
CA (n)
Read
CA (n + 4)
Bank active
RA
RA
92CH21-385
D (n)
CA (n + 8)
85 states (320-byte read)
3 states
OUT
D (n + 4)
CA (n + 12)
precharge
Write with
D (n + 8)
CA
CA
precharge
D (n + 12)
Internal
(n + 312)
(n + 316)
D (n + 312) D (n + 316)
precharge
All banks
TMP92CH21
2009-06-19

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