TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 362

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TMP92xy21FG

Manufacturer Part Number
TMP92xy21FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy21FG

Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
16
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
1
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
1
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
82
Power Supply Voltage(v)
3.0 to 3.6
LD bus output sequence
8 bits (TFT)
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LSB
D0
LSB
D0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
0
0 (R1) → 8 (R2)
1 (R1) → 9 (R2)
2 (R1) → 10 (R2) ...
3 (G1) → 11 (G2) ...
4 (G1) → 12 (G2) ...
5 (G1) → 13 (G2) ...
6 (B1) → 14 (B2) ...
7 (B1) → 15 (B2) ...
R1
R5
1
*
2
Address 0
Address 4
When using 256-color TFT mode, 8-bit LD bus width must be used.
LD8, LD9, LD10 and LD11 terminals are available for use as general ports.
3
G1
G5
4
Figure 3.14.15 Relation of Memory Map Image and Output Data (5)
5
Relation of memory map image and output data
6
...
...
B1
B5
256 colors (8 bpp; R: 3 bits, G: 3 bits, B: 2 bits)
Display memory image
7
8
R2
R6
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Address 1
Address 5
G2
G6
92CH21-360
B2
B6
R3
R7
Address 2
Address 6
G3
G7
B3
B7
R4
R8
Address 3
Address 7
TMP92CH21
G4
G8
2009-06-19
B4
B8
MSB
MSB
D31
D31

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