TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 258

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(c-3-2) OUT status stage
The transaction format for OUT status stage is given below.
Control flow
normally, the UDC sets error to STATUS register.
normally, the UDC sets error to STATUS register. For sequence of this
protocol, refer to section supplement.
It finishes normally by the above transaction.
If a time out occurs without receiving ACK from host,
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At this point, if new SETUP stage is started without status stage finishing
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The transaction flow for OUT status stage in the UDC is given below.
It finishes normally by the above transaction.
If there is an error in data, ACK handshake is not returned.
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At this point, if new SETUP stage is started without status stage finishing
4.
1.
2.
3.
4.
Set STATUS register to TX_ERR and state returns to IDLE, and wait for
restring status stage.
Token: OUT
Data: DATA1 (0 data length)
Handshake: ACK, NAK, STALL
Set RX_ERR to STATUS register and return to IDLE. It waits to retry
status stage.
If ACK handshake from host is received,
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Token packet is received and address, endpoint number and error are
confirmed. If they do not correspond, the state returns to IDLE. If
status stage is enabled based on stage control flow in the UDC,
advance to next stage.
STATUS register state is confirmed.
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Whether EOP register is accessed or not is confirmed externally. If it
is not accessed, NAK handshake is returned to continue control
transfer, and state returns to IDLE.
If EOP register access is confirmed, 0-data-length data packet and
CRC are received.
If there is no error in data, ACK handshake is transmitted to host.
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Set STATU to READY.
Assert INT_STATUS interrupt.
INVALID condition: State returns to IDLE.
STALL condition: Data is cleared, stall handshake is returned,
Set STATUS to READY.
Assert INT_STATUS interrupt.
92CH21-256
and state returns to IDLE.
TMP92CH21
2009-06-19