TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 349

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

LCDSCC
(0287H)
3.14.3.5 Refresh Rate Setting
* Data should be written from 1-hex to FFFF-hex in the above register. It cancannot operate if set
* If the refresh rate is set too fast, it may not be in time with the display data. t
Bit symbol
Read/Write
Reset State
Function
to “0”.
by SCC.
and FP [9:0] (LCDCTL0<FP9, 8>, LCDFFP<FP7:0>). The LBCD terminal outputs one
pulse every cycle and the LFR normally outputs an inverted signal every cycle. But
when the DIVIDE FRAME function is used, the LFR signal changes to a special signal
for high quality display.
(1) Basic clock setting
t
during t
data transmission time.
t
LP
LP
Frame cycle (refresh rate) is generated from setting of LSCC (LCDSCC<SCC7:0>)
[s] = (1/f
is shown in 1-line (ROW) display time. 1-line data transmission must be completed
controller. This generator can set details of the refresh rate for the LCDC.
f
FP: FP [9:0] setting value of FFP register
SCC: <SCC7:0> setting value of LSCC register
Example:
Value of setting to register is only integer, SCC = 17. The floating value is disregarded.
In this case, the refresh rate comes to 144.6 [Hz]
BCD
SCC7
This LSI has a special clock generator for basic source clock used in the LCD
This generator is made by dividing the system clock by 16 and an 8-bit counter.
The following shows the method of setting and calculation.
LP
0
7
[Hz]: Frame rate (Refresh rate: Frequency of LBCD signal)
f
f
140 [Hz] = 20000000 [Hz]/((SCC+1) × 16 × 480)
(SCC+1) = 20000000/(140 ×16 × 480) = 18.60
BCD
SYS
cycle time. AboutRefer to “Data transmission and bus occupation” for details of
SYS
[Hz] = 20MHz, 480COM (FP = 480), target refresh rate = 140Hz
[Hz] = f
LCDC Source Clock Counter Register
[Hz]) × 16 × (SCC + 1)
SCC6
0
6
SYS
[Hz] / ((SCC+1) × 16 × FP)
SCC5
92CH21-347
0
5
LCDC Source Clock Counter bit7 to bit0
SCC4
0
4
R/W
SCC3
0
3
SCC2
0
2
LP
SCC1
time is determined
0
1
TMP92CH21
2009-06-19
SCC0
0
0