TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 501

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
P8FC2
P9FC2
P7CR
P9CR
P7FC
P8FC
P9FC
(1) I/O ports (3/7)
register2
register2
function
function
function
function
function
Name
register
register
register
register
register
control
control
Port 7
Port 7
Port 8
Port 8
Port 9
Port 9
Port 9
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
001EH
001FH
0023H
0021H
0026H
0027H
0025H
RMW)
RMW)
RMW)
RMW)
RMW)
RMW)
RMW)
0: Input port
1: INT5
0: Port
1: CSZE
0: <P87F>
1: SRUUB
P87F2
P87F
P97F
7
0
0
0
0: Input
1: Output
0: Port
1: WAIT
0: Port
1: CSZD
0: <P86F>
1: SRULB
0: Input port
1: INT4
WAIT
P86F2
P76C
P76F
P86F
P96F
W
6
0
0
0
0
0
port,
port
92CH21-499
1: LGOE2
1: Output
0: Port
1: NDR/
0: Port,
1: CSZC ,
0: Port,
1: WRUU ,
0: Output
0: Input
0: Output
CLK32KO
1:
CLK32KO
NDR/
R/ W
LGOE2
P85F2
R/ W
P75C
P95C
P75F
P85F
WRUU
ND
CSZC
ND
P95F
port,
W
port,
5
0
0
0
0
0
0
1
1
CE
CE
port,
port,
B
B
,
1: Output
0: Port
1: EA25
0: Port,
1: CSZB ,
0: Port,
1: WRUL ,
0: Input
0: Port
1: LGOE1
LGOE1
P84F2
WRUL
CSZB
P94C
P74F
P84F
P94F
ND
ND
port,
4
0
0
0
0
0
port
0
0
CE
CE
W
W
W
0: Port
1: LGOE0
0: Port
1: EA24
0: Port
1:
Always write
“0”
0:Input
1: Output
LGOE0
P93C
P73F
P83F
P93F
CS
port,
W
3
0
0
−
0
0
0
3
port
W
0: Input port,
1: Output
<P72> = 0,
<P72> = 1
NDWE @
0: Port
1: NDWE ,
0: Port,
1:
0: Port
1: CSZA
0:Input
1: I2SWS,
0: Port,
1: I2SWS,
WRLH @
SCLK0,
P82F2
CTS
SCLK0
SCLK0,
SCLK0
CSZA
CS ,
SDCS
CTS
P72C
P92C
P72F
WRLU
P82F
P92F
port,
W
2
0
0
0
0
0
0
2
port,
0
0
<P71> = 0,
<P71> = 0
1: I2SDO
NDRE @
WRLL @
0: Input port
1: Output
0: Port
1: NDRE ,
0: Port
1:
0: <P81F>
1: SDCS
0: Input
1: Output
0: Port,
RXD0,
I2SDO
P81F2
RXD0
P71C
P91C
P71F
WRLL
P81F
P91F
CS
port,
W
1
0
0
0
0
0
0
port,
1
port
TMP92CH21
2009-06-19
0: Port
1: I2SCKO,
0: Port
1: RD
0: Port
1:
Always write
“0”
0: Input
1: Output
0: CMOS
1: Open
P90FC2
I2SCKO
TXD0
TXD0
drain
P90C
P70F
P80F
P90F
CS
0/1
port,
port,
W
0
0
−
0
0
0
0
0