TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 100

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

PG
(0040H)
PGDR
(0090H)
3.5.13
Note: The input channel selection of the AD converter and the permission for ADTRG input are set by AD converter mode
Bit symbol
Read/Write
Reset State
Bit symbol
Read/Write
Reset State
Function
Port G (PG0 to PG3)
internal AD converter. PG3 can also be used as the ADTRG pin for the AD converter.
register ADMOD1.
PG0 to PG3 are 4-bit input ports and can also be used as the analog input pins for the
PG2 and PG3 can also be used as the MX and MY pins for a touch screen interface.
7
7
(only for PG3)
Port G read
AD read
ADTRG
6
6
Figure 3.5.37 Register for Port G
Conversion
register
Port G Drive Register
Figure 3.5.36 Port G
result
Port G Register
5
5
92CH21-98
converter
AD
4
4
Switch for TSI
typ. 20 Ω
register for standby mode
Input/Output buffer drive
PG3D
PG2
Channel
selector
3
3
1
R/W
Data from external port
PG2D
PG2
2
2
1
(Only for PG2, PG3)
TSICR0<MXEN, MYEN>
TSICR0<TSI7>
PG0 (AN0),
PG1 (AN1),
PG2 (AN2, MX),
PG3 (AN3, MY,
R
PG1
1
1
TMP92CH21
2009-06-19
ADTRG
PG0
0
0
)