TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 344

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.14.3.3 Display Memory Mapping and Panning Function (Common spec. SR mode and TFT mode)
3.14.3.4 Data Transmission
B and C areas. The display area can be panned vertically and horizontally by changing
the row address and column address.
grayscales), 3 bpp (8 grayscales), 4 bpp (16 grayscales), 8 bpp (256 colors) and 12 bpp
(4096 colors) and 1-line (row). Data volume is different for each display mode. When
using the panning function, care must be exercised in calculating the address for each
display mode. For details, refer to Figure 3.14.2 to Figure 3.14.5, “Relation of memory
map image and output data”. This LCDC can also support external SDRAM, SRAM
and internal SRAM for display RAM.
input continuously in display RAM, even if the panning function is not used. One row
address of display SDRAM corresponds to the first line of the display panel. Second
line display data cannot now be set within the first row address of the display RAM
even if the necessary data for the size you want to display does not fill the capacity of
first row address of the display SDRAM. Adding one line to the display panel is equal
to adding one address to the row address of the display SDRAM. In other words, when
using SDRAM for display RAM, address calculation for panning is simple.
input continuously to the display RAM. However, address calculation for panning is
complex and horizontal panning function is not supported.
of 4-or 8-bits can be supported, and 2 formats selected for each bus width . The 2
formats of 8-bit bus width can support only STN color mode (256, 4096 colors). The
12-bit bus width supports only TFT mode.
all LD bus data is inverted. There is <AUTOINV> bit in this LCDMODE2 register, but
this automatic data invert function is only for TFT mode.
The LCDC can only change the panel window if you change each start address of A,
This LCDC can select many display modes: 1 bpp (monochrome), 2 bpp (4
When using SDRAM for display RAM, data from one line to the next line cannot be
When using SRAM for display RAM, data from one line to the next line must be
This LSI has an LD bus (LD7 to LD0): a special data bus for LCD driver. Bus width
LD bus data invert function is also supported. By setting LCDMODE2<LDINV> = 1,
92CH21-342
TMP92CH21
2009-06-19