TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 15

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.1.2
VCC (3.3 V)
RESET
Reset Operation
operating voltage range, and that the internal high-frequency oscillator has stabilized.
Then hold the
system clock operates at 1.25 MHz (fc = 40 MHz).
program counter settings. CPU internal registers not mentioned above do not change when
the reset is released.
after power-on reset. External RAM data provided before turning on the TMP92CH21 may
be corrupted because the control signals are unstable until the power supply becomes
stable after power on reset.
When resetting the TMP92CH21, ensure that the power supply voltage is within the
At reset, since the clock doubler (PLL) is bypassed and the clock-gear is set to 1/16, the
When the reset has been accepted, the CPU performs the following:
When the reset is released, the CPU starts executing instructions according to the
When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
Internal reset is released as soon as external reset is released.
Memory controller operation cannot be ensured until the power supply becomes stable
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Sets the stack pointer (XSP) to 00000000H.
Sets bits <IFF2:0> of the status register (SR) to 111 (thereby setting the interrupt
level mask register to level 7).
Clears bits <RFP1:0> of the status register to 00 (there by selecting register bank
0).
Initializes the internal I/O registers as shown in the “Special Function Register”
table in section 5.
Sets the port pins, including the pins that also act as internal I/O, to
general-purpose input or output port mode.
Sets the program counter (PC) as follows in accordance with the reset vector stored
at address FFFF00H to FFFF02H:
PC<7:0>
PC<15:8>
PC<23:16>
High-frequency oscillation stabilized time
RESET
Figure 3.1.1 Power on Reset Timing Example
+20 system clock
input low for at least 20 system clocks (16 µs at fc = 40 MHz).
← data in location FFFF00H
← data in location FFFF01H
← data in location FFFF02H
92CH21-13
0 s (Min)
TMP92CH21
2009-06-19