TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 226

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Request Mode
(07D9H)
3.10.3.20 Request Mode Register
bit Symbol
Read/Write
Reset State
−
Soft_Reset
G_Port_Sts
G_Config
G_Descript
Note: The TMP92CH21 does not use this register since it does not support printer-class.
Note1: SET_ADDRESS request is supported only by auto-answer .
Note2: SET_DESCRIPTOR and SYNCH_FRAME are controlled only by software .
Note3: Vendor Request and Class Request (Printer Class and so on) are controlled only by software.
Note4: INT_SETUP, ENDPOINT0, STATUS and STATUSNAK interrupts assert only when it is software-control.
by control through software. Each bit represents a kind of request.
by hardware. When relevant bit in this register is set to “1”, the answer is controlled
by software. If a request is received during hardware control, the interrupt signal
(INT_SETUP, INT_ENDPOINT0, INT_STATUS, INT_STATUSNAK) is set to disable.
If a request is received during software control, the interrupt signal is asserted, and it
is controlled by software.
This register sets the answer for Class Request either automatically in hardware or
When relevant bit in this register is set to “0”, the answer is executed automatically
7
Soft_Reset
(Bit 7)
(Bit 6)
(Bit 5)
(Bit 4)
(Bit 3 to 0) : Reserved
R/W
6
0
G_Port_Sts
: Reserved
: SOFT_RESET
: GET_PORT_STATUS
: GET_DEVICE_ID
92CH21-224
R/W
5
0
G_DeviceId
R/W
4
0
3
2
1
TMP92CH21
2009-06-19
0