TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 20

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(Operate oscillator and PLL)
The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called
fs. The clock frequency selected by SYSCR1<SYSCK> is called the clock f
clock of f
Note 1: It is not possible to control PLL in SLOW mode when shifting from SLOW mode to NORMAL mode with use of PLL.
Note 2: When shifting from NORMAL mode with use of PLL to NORMAL mode, execute the following setting in the same order.
Note 3: It is not possible to shift from NORMAL mode with use of PLL to STOP mode directly.
(I/O operate)
IDLE2 mode
IDLE1 mode
(Operate only oscillator)
(Operate only oscillator)
(Operate only oscillator)
(Operate only oscillator)
clock mode (X1, X2, XT1 and XT2 pins) and (c) triple clock mode (X1, X2, XT1 and XT2 pins and
PLL).
FPH
The clock operating modes are as follows: (a) single clock mode (X1, X2 pins only), (b) dual
Figure 3.3.1 shows a transition figure.
(PLL start up/stop/change write to PLLCR0<PLLON>, PLLCR1<FCSEL> register)
1) Change CPU clock (PLLCR0<FCSEL> ← “0”)
2) Stop PLL circuit (PLLCR1<PLLON> ← “0”)
PLL.)
(I/O operate)
(I/O operate)
(I/O operate)
(I/O operate)
NORMAL mode should be set once before shifting to STOP mode. (Sstop the high-frequency oscillator after stopping
IDLE2 mode
IDLE1 mode
IDLE2 mode
IDLE1 mode
IDLE2 mode
IDLE1 mode
IDLE2 mode
IDLE1 mode
, and one cycle of f
Instruction
Interrupt
Interrupt
Instruction
SYS
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
Instruction
Interrupt
is defined as one state.
Instruction
Figure 3.3.1 System Clock Block Diagram
Note
(4 × f OSCH /gear
NORMAL mode
(a)
Using PLL
(b)
(c)
value/2)
Single clock mode transition figure
Dual clock mode transition figure
Triple clock mode transition figure
Instruction
Instruction
(f OSCH /gear value/2)
(f OSCH /gear value/2)
(f OSCH /gear value/2)
(Stops all circuits)
92CH21-18
NORMAL
NORMAL
NORMAL mode
SLOW mode
STOP mode
(f
(f
(f
OSCH
OSCH
OSCH
Instruction
Reset
Reset
Reset
(fs/2)
Instruction
Note
Release reset
Release reset
Release reset
/32)
/32)
mode
/32)
mode
Interrupt
Interrupt
Interrupt
FPH
SLOW mode
Instruction
Interrupt
Instruction
Instruction
Interrupt
Interrupt
. The system clock f
(fs/2)
Instruction
Instruction
Instruction
Interrupt
Interrupt
SYS
(Stops all circuits)
(Stops all circuits)
(Stops all circuits)
is defined as the divided
STOP mode
STOP mode
STOP mode
(Operate only oscillator)
(I/O operate)
IDLE2 mode
IDLE1 mode
TMP92CH21
2009-06-19