TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 259

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(c-4) Stage management
register. Each stage in control transfer type has to process combination software.
UDC detects the following contents from 8-byte data in SETUP stage. The stage is
managed by determining control transfer type.
write transfer type, or control write transfer type (No data stage).
state of internal UDC, NAK handshake is returned and BUSY is informed to USB
host. In all control transfer types, if SETUP token is received from host, present
transaction is stopped, and it switches to SETUP stage in the UDC. The CPU
receives new INT_SETUP even if it is processing previous control transfer.
The UDC manages each stage of control transfer by hardware.
Each stage is changed by receiving token from USB host, or CPU accesses
Based on these it is determined to be either control read transfer type, control
Various conditions for changing stage in control transfer are given below.
If receiving token for next stage from host before switching to next stage from
•
•
Whether there is data stage or not
Data stage direction
92CH21-257
TMP92CH21
2009-06-19