TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 70

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

P1CR
(0006H)
P1FC
(0007H)
P1DR
(0081H)
P1
(0004H)
Note1: Read-modify-write is prohibited for P1CR and P1FC.
Note2: It is set to “Port” or “Data bus” by AM pin setting.
Bit symbol
Read/Write
Reset State
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
P17C
P17D
P17
7
7
7
7
0
1
P16C
P16D
P16
6
6
6
6
0
1
Figure 3.5.2 Register for Port 1
Data from external port (Output latch register is cleared to “0”)
Port 1 Function register
Port 1 Control register
Input/Output buffer drive register for standby mode
Port 1 Drive register
P15C
P15D
P15
5
5
0
5
5
1
Port 1 register
92CH21-68
P14C
P14D
0: Input 1: Output
P14
4
4
4
0
4
1
R/W
W
W
P13C
P13D
P13
3
3
3
0
3
1
P12C
P12D
P12
2
2
2
0
2
1
P11C
P11D
P11
1
1
1
0
1
1
TMP92CH21
2009-06-19
0: Port
1: Data bus
(D8 to D15)
0/1 Note 2
P10C
P10D
P10
P1F
W
0
0
0
0
1
0