TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 334

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Display color
The number of picture
elements which can be
handled
Maximum transmission rate
(Destination: LCD driver)
(VRAM: RAM, SDRAM)
3.14.1
(at f
Data bus width
Data bus width
LCD driver
Pan function
SYS
LGOE2 to LGOE0
LCD data bus
= 20 [MHz])
LD11 to LD0
Address bus
Bus state
D7 to D0
LBCD
LCP0
LCP1
LCDC features by Mode
Table 3.14.1 LCDC features by Mode (example: T6C13B, T6B66A by Toshiba)
LDIV
R/W
LLP
LFR
A0
The various features and pin operations of are as follows.
Row (Common):
Column (Segment):
Internal SRAM: 256 to 128 × 128 max, 4096 to 128 × 64 max
12.5 ns/bytes at internal RAM, 25 ns/byte at external SRAM
Horizontal shift clock for
source driver of TFT panel
Vertical shift clock for gate
driver of TFT panel
Data load signal for source
driver of TFT panel
Output enable signal for gate
driver of TFT panel
Alternating signal for LCD
display control.
Connect to FR pin of LCD
driver.
Connect to LDIV pin for
source driver of TFT panel.
This signal shows output
data inversion.
64, 128, 160, 200, 240, 320
64, 128, 160, 256, 320
256 colors, 4096 colors
Connect to data bus of LCD driver.
16 bits, 32 bits
8 bits, 12 bits
• 4-bit LD3 to LD0
• 8-bit LD7 to LD0
• 12-bit LD11 to LD0 (Only use TFT panel)
Shift Register Type LCD Driver Control Mode
TFT
12.5 ns/byte at SDRAM/BURST
92CH21-332
Available to use
256 colors, 4096 colors
Shift clock 0 for column LCD driver
Connect to CP pin of column LCD driver.
LD bus data is latched at falling edge of this
signal.
Shift clock 1 for column LCD driver
Connect to CP pin of column LCD driver.
LD bus data is latched at falling edge of this
signal.
Latch pulse output for column and row LCD
driver
Connect to LP pin of column and row LCD
driver. Display data is renewed to output
buffer at rising edge of this signal.
Alternating signal for LCD display control.
Connect to FR pin of LCD driver.
Refresh rate signal
Monochrome, 4-, 8- and16-level grayscale
Monochrome, 4-, 8- and16-level grayscale
Row (Common):
64, 128, 160, 200, 240, 320, 480
Column (Segment):
64, 128, 160, 256, 320, 480, 640, 768, 960
Row (Common):
64, 128, 160, 200, 240, 320
Column (Segment):
64, 128, 160, 256, 320
Not used
Not used
Not used
256 colors, 4096 colors
16 bits, 32 bits
4 bits, 8 bits
Not used
STN
Not use
(Same as normal
memory access)
Depends on LCD driver
Connect to data bus of
LCD driver.
Connect to
LCD driver.
Connect to D/I pin of
LCD driver for distinction
of data or instruction.
Chip enable signal for
column LCD driver
Connect to
column LCD driver.
Chip enable signal for
column LCD driver
Connect to
2nd column LCD driver.
Chip enable signal for
column LCD driver
Connect to
3rd column LCD driver.
Chip enable signal for
row LCD driver
Connect to
row LCD driver.
LCD Driver Control
Depends on LCD driver
Depends on LCD driver
RAM Built-in Type
Depends on CS/WAIT
controller
Not used
Not used
Not used
Mode
TMP92CH21
2009-06-19
−
CE
WR
CE
CE
LE
pin of 1st
pin of
pin of
pin of
pin of