TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 130

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.7.2
System clock
xxx: Don’t care
<SYSCK>
selection
SYSCR1
1(fs)
0(fc)
Operation of Each Circuit
(1) Prescalers
(2) Up counters (UC0 and UC1)
timer control register. Setting <TA01PRUN> to “1” starts the count; setting
<TA01PRUN> to “0” clears the prescaler to “0” and stops operation. Table 3.7.2 shows
the various prescaler output clock resolutions.
specified by TA01MOD.
the TA0IN pin or one of the three internal clocks φT1, φT4 or φT16. The clock setting is
specified by the value set in TA01MOD<TA01CLK1:0>.
overflow output from UC0 is used as the input clock. In any mode other than 16-bit
timer mode, the input clock is selectable and can either be one of the internal clocks
φT1, φT16 or φT256, or the comparator output (the match detection signal) from
TMRA0.
TA01RUN<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the up
counters and to control their count. A reset clears both up counters, stopping the
timers.
A 9-bit prescaler generates the input clock to TMRA01.
The clock φT0 is divided into 8 by the CPU clock f
The prescaler operation can be controlled using TA01RUN<TA01PRUN> in the
These are 8-bit binary counters which count up the input clock pulses for the clock
The input clock for UC0 is selectable and can be either the external clock input via
The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the
For
<GEAR2:0>
100 (1/16)
Clock gear
000 (1/1)
001 (1/2)
010 (1/4)
011 (1/8)
SYSCR1
selection
−
each
Table 3.7.2 Prescaler Output Clock Resolution
interval
1/8
−
φT1(1/2)
timer
92CH21-128
fc/128
fc/256
fs/16
fc/16
fc/32
fc/64
the
Timer counter input clock
TAxMOD<TAxCLK1:0>
φT4(1/8)
timer
fc/1024
fc/128
fc/256
fc/512
fs/64
fc/64
TMRA prescaler
operation
SYS
φT16(1/32) φT256(1/512)
and input to this prescaler.
fc/1024
fc/2048
fc/4096
fs/256
fc/256
fc/512
control
fc/16384
fc/32768
fc/65536
fs/4096
fc/4096
fc/8192
register
TMP92CH21
2009-06-19
bits