TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 176

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

SC1CR
(1209H)
Bit symbol
Read/Write
Reset State
Function
Note: As all error flags are cleared after reading do not test only a single bit with a bit testing instruction.
data bit8
Received
Undefined
RB8
Figure 3.9.10 Serial Control Register (Channel 1, SC1CR)
7
R
Parity
0: Odd
1: Even
EVEN
6
0
R/W
Parity
addition
0: Disable
1: Enable
PE
92CH21-174
5
0
Overrun
OERR
4
0
R (cleared to 0 when read)
1: Error
PERR
Parity
3
0
I/O interface input clock select
Edge selection for SCLK pin (Input/Output mode)
Framing error flag
Parity error flag
Overrun error flag
Parity additions enable
Even parity addition/check
Received data bit8
0
1
0
1
0
1
0
1
Baud rate generator
SCLK1 pin input
Transmits and receives
data on rising edge of SCLK1.
Transmits and receives
data on falling edge of SCLK1.
Disabled
Enabled
Odd parity
Even parity
Framing
FERR
2
0
0: SCLK1
1: SCLK1
SCLKS
1
0
Cleared to 0
when read
TMP92CH21
R/W
2009-06-19
0: Baud rate
1: SCLK1
generator
pin input
IOC
0
0