TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 253

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(b) Interrupt transfer type
(b-1) Interrupt transmitting mode (Toggle mode)
(b-2) Interrupt transmission mode (Not toggle mode)
transfer.
the same as for transmission bulk transfer. Interrupt transfer can be transferred
without using toggle bit. In this case, if ACK handshake from host is not received,
toggle bit is renewed, and finish is normal. The UDC clears FIFO for next transfer.
Interrupt transfer type uses the same transaction format as transmission bulk
For transmission using toggle bit, hardware setting and answer in the UDC are
When ACK handshake from host is received after transmission of data packet,
Clear FIFO.
UDC finishes normally by above transaction. FIFO can receive next data.
If a time out occurs without receiving ACK from host,
Execute above setting. This setting is the same except for STATUS changes.
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(a).
handshake from host is not received, transaction is different.
UDC operation is same as in bulk transmission mode. Please refer to section
This is basically the same as bulk transmission mode. However, if ACK
Clear DATASET register.
Renew toggle bit and prepare for next.
Set STATUS to READY.
Clear FIFO.
Clear DATASET register.
Renew toggle bit and prepare for next.
Set STATUS to TX_ERR.
92CH21-251
TMP92CH21
2009-06-19