TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 319

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Read
-modify
-write
instruction is
prohibited
WDMOD
(1300H)
WDCR
(1302H)
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
WDT control
1: Enable
WDTE
B1H: WDT disable code
4EH: WDT clear code
7
1
7
Figure 3.12.5 Watchdog Timer Control Register
Figure 3.12.4 Watchdog Timer Mode Register
Select detecting time
00: 2
01: 2
10: 2
11: 2
WDTP1
R/W
6
15
17
19
21
6
0
/f
/f
/f
/f
IO
IO
IO
IO
WDTP0
92CH21-317
5
5
0
4
4
W
Watchdog timer out control
IDLE2 control
Watchdog timer detection time
Watchdog timer enable/disable control
−
−
00
01
10
11
Always
write “0”
0
1
0
1
0
1
Others
B1H
4EH
−
Connects WDT out to a reset
Stop
Operation
Disabled
Enabled
3
2
2
2
2
3
−
0
15
17
19
21
WDT disable/clear control
/f
/f
/f
/f
IO
IO
IO
IO
(Approximately 3.28 ms at f
(Approximately 13.1 ms at f
(Approximately 52.4 ms at f
(Approximately 210 ms at f
Disable code
Clear code
Don’t care
IDLE2
0: Stop
1: Operate
I2WDT
2
2
0
R/W
1: Internally
connects
WDT out
to the
reset pin
RESCR
1
1
0
TMP92CH21
2009-06-19
OSCH
OSCH
OSCH
OSCH
Always
write “0”
= 40 MHz)
= 40 MHz)
= 40 MHz)
= 40 MHz)
0
0
−
0