TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 374

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.14.6.3 Sequential Access Type
Bit symbol
Read/Write
Reset State
Function
Figure 3.14.22 Example of Access Timing for Built-in RAM Type LCD Driver (Wait = 0)
LCDC0L/LCDC0H/LCDC1L/LCDC1H/LCDC2L/LCDC2H/LCDR0L/LCDR0H Register
Note 1: This waveform is in the case of 3-state access.
Note 2: Rising timing of chip enable signal (e.g LCP0) is different.
CPU.
instruction is executed the LCDC outputs a chip select signal to the LCD driver
connected externally by the control pin (LCP0...). Therefore control of data
transmission numbers corresponding to LCD size is controlled by CPU instruction.
There are 2 kinds of LCD driver address in this case, which are selected by the
LCDCTL<MMULCD> register.
display data register in LCD driver when <MMULCD> = “0”. Please select the
transmission address at this time from 1FE0H to 1FE7H.
Data transmission to the LCD driver is executed by a transmit instruction from the
After setting operation mode to the control register, when a CPU transmit
This corresponds to a LCD driver which has each 1 byte of instruction register and
D7
System clock: f
7
LCP0, LLP,
LFR, LBCD
A23 to A0
D7 to D0
D6
R/
6
SYS
W
D5
5
92CH21-372
Depends on external LCDD specification
Depends on external LCDD specification
Depends on external LCDD specification
T1
WAIT sampling
[Write cycle]
Data out
TW
D4
4
T2
D3
3
D2
2
T1
[Read cycle]
TW
D1
1
Data in
TMP92CH21
T2
2009-06-19
D0
0