TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 516

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
LCDMODE0
LCDMODE1
LCDDVM
LCDSIZE
LCDFFP
LCDCTL0
LCDCTL1
(6) LCD controller (1/6)
divide FRM
LCD frame
frequency
LCD size
control 0
control 1
Name
mode 0
register
mode 1
register
register
register
register
register
register
LCD
LCD
LCD
LCD
LCD
Address
0280H
0281H
0282H
0283H
0284H
0285H
0286H
RAMTYPE1 RAMTYPE0
Common setting
0000: Reserved
0001: 64
0010: 120
0011: 128
Display RAM
00: Internal SRAM
01: External SRAM
10: SDRAM
11: Reserved
0100: 160 Others: Reserved
LCP0
phase
0: Rising
1: Falling
LCP0P
COM3
FMN7
FP7
R/W
0
0
0
7
0
1
Column
Data
setting
0: Normal
1: All
LCP1
phase
0: Rising
1: Falling
LCP1P
COM2
FMN6
display
data “0”
ALL0
FP6
R/W
0
0
0
6
0
0
0
0101: 200
0110: 240
0111: 320
1000: 480
92CH21-514
LD bus transmission
speed
00: Reserved
01: 2 × f
10: 4 × f
11: 8 × f
LLP mode
0: mode1
1: mode2
FR divide
setting
0: Disable
1: Enable
LBCD
phase
0: Low
1: High
LLPMODE
FRMON
LBCDP
SCPW1
COM1
FMN5
FP5
R/W
0
0
0
5
1
0
0
0
SYS
SYS
SYS
Setting DVM bit7 to bit0
LD bus
inversion
0: Normal
1: Inversion
Always
write “0”
Setting bit7 to bit0 f
SCPW0
COM0
FMN4
LDINV
FP4
0
0
0
4
0
0
−
0
R/W
R/W
R/W
R/W
Segment setting
0000: Reserved 0101: 320
0001: 64
0010: 128
0011: 160
Mode setting
0000: Built-in RAM type
0001: SR 1bpp (mono)
0010: SR 2bpp (4gray)
0011: SR 3bpp (8gray)
0100: SR 4bpp (16gray)
Auto LD
bus
inversion
0: Disable
1: Enable
(Valid in
TFT mode)
0100: 256 1001: 960 Others: Reserved
f
bit
FP setting
AUTOINV
MODE3
FMN3
SEG3
9
R/W
FP3
FP9
0
0
0
3
0
0
0
FP
R/W
Select
interrupt
0: LP
1: BCD
Built-in
RAM LCDD
setting
0:
Sequential
access
1: Random
MMULCD
INTMODE
MODE2
access
FMN2
SEG2
FP2
0
0
0
2
0
0
0
0110: 480
0111: 640
1000: 768
0101: STN 8bpp (256)
0110: STN 12bpp (4096)
0111: Reserved
1000: TFT 8bpp (256)
1001: TFT 12bpp (4096)
Others: Reserved
LD bus width control
00: 4bit width A_type
01: 4bit width B_type
10: 8bit width A_type
11: 8bit width B_type
Others: Reserved
f
bit 8
LBCD width control
00: LCP1_1CLK
01: LCP1_2CLK
10: LCP1_3CLK
11: Reserved
LBCDW1
FP setting
MODE1
FMN1
SEG1
LDO1
R/W
FP1
FP8
0
0
0
1
0
0
0
0
TMP92CH21
2009-06-19
LCDC start
0: STOP
1: START
LBCDW0
START
MODE0
FMN0
SEG0
LDO0
R/W
FP0
0
0
0
0
0
0
0
0