TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 131

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(3) Timer registers (TA0REG and TA1REG)
set in the timer register TA0REG or TA1REG matches the value in the corresponding
up counter, the comparator match detect signal goes Active. If the value set in the
timer register is 00H, the signal goes Active when the up counter overflows.
buffer structure is enabled or disabled. It is disabled if <TA0RDE> = “0” and enabled if
<TA0RDE> = “1”.
timer register when a 2
in PPG mode. Hence the double buffer cannot be used in timer mode.
buffer, write data to the timer register, set <TA0RDE> to “1”, and write the following
data to the register buffer. Figure 3.7.3 show the configuration of TA0REG.
Note: The same memory address is allocated to the timer register and the register buffer.
These are 8-bit registers, which can be used to set a time interval. When the value
TA0REG has a double buffer structure, making a pair with the register buffer.
The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG’s double
When the double buffer is enabled, data is transferred from the register buffer to the
A reset initializes <TA0RDE> to “0”, disabling the double buffer. To use the double
Timer registers 0 (TA0REG)
The address of each timer register is as follows.
All these registers are write only and cannot be read.
When <TA0RDE> = 0, the same value is written to the register buffer and the timer
register; when <TA0RDE> = 1, only the register buffer is written to.
Register buffers 0
Internal data bus
TA0REG: 001102H
TA2REG: 00110AH
Figure 3.7.3 Configuration of TA0REG
Shift trigger
Write
n
overflow occurs in PWM mode, or at the start of the PPG cycle
92CH21-129
TA1REG: 001103H
TA3REG: 00110BH
TA01RUN<TA0RDE>
Selector
S
B
A
Matching detection PPG cycle
2
Write to TA0REG
n
overflow of PWM
TMP92CH21
2009-06-19