TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 393

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.16.3
Take care to note the following points when using SDRAMC.
1.
2.
3.
4.
Note : * When using SDRAM as a stack pointer, it is necessary to disable SDRAM access by, for example, a “DI”
Limitations arising when using SDRAM
SDRAM. In WAIT-pin input setting of the Memory Controller, if the setting time is
inserted as an external WAIT, set a time less than the Auto-Refresh cycle × 14 (Auto-
Refresh function controlled by SDRAM controller).
several states are required for execution time after the SDCMM register is set.
insert a NOP of more than 10 bytes or 10 other instructions before executing the HALT
instruction.
frequency for the SDRAM and minimum refresh cycle.
in AR cycle for SDRAM.
Auto-Refresh. Therefore, set Auto-Refresh cycle after adding 10 states to distibuted
Auto-Refresh cycle.
Auto-Refresh, please stop Auto-Refresh once.
be used as below.
When using SDRAM, some limitation is added when accessing memory other than
When a SDRAM controller command (SR-Entry, Initialize and Mode-set) is issued,
Therefore, when a HALT instruction is executed after the SDRAM command, please
When using SDRAM, set the system clock frequency to satisfy the minimum operation
In a system in which SDRAM is used and the clock is geared up and down,exercise care
When AR cycle is changed, set to disable by writing “0” to SDRCR<SRC>.
The AR cycle may also not correspond to the SDRAM A.C specification when stopping
In order to prevent a conflict between a Self-Refresh ENTRY command and an
A) Disable Auto Refresh before writing Self Refresh ENTRY command.
B) Enable Auto Refresh after writing Self Refresh ENTRY command.
Because the above instruction should be executed continuously, a 16-bit instruction must
(Example of recommended settings)
WAIT access
Execution of SDRAM command before HALT instruction (SR (Self refresh)-Entry,
Initialize, Mode-set)
AR (Auto-Refresh) interval time
Self-Refresh ENTRY method
*DI
LDW
LD
(Example of calculation)
Condition:
64ms/ 4096times = 15.625us/1time = 187.5state/1time
187.5 − 10 = 177.5state/less than 1 time is needed → 156 state is needed
instruction.
f
SDRAM specification of distributed Auto-Refresh interval time =4096times/64ms
SYS
=12MHz,
(SDRCR),0000010100000010B
(SDRCR),0000---1B
92CH21-391
;
;
Disable AR → SR-ENTRY
Enable AR
TMP92CH21
2009-06-19