TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 121

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.6.4
D0 to D31
A0 to A23
SDCLK
ROM Control (Page mode)
mode is set by the page ROM control register.
(1) Operation and how to set the registers
CS
RD
This section describes ROM page mode accessing and how to set registers. ROM page
2
mode is specified only in block address area 2.
<OPGE> of the PMEMCR register to “1” sets the memory access of the block address
area to ROM page mode access.
the PMEMCR register. When data is read out up to the border of the set page, the
controller completes the page reading operation. The start data of the next page is read
in the normal cycle. The following data is set to page read again.
The TMP92CH21 supports ROM access of the page mode. ROM access of the page
ROM page mode is set by the page ROM control register (PMEMCR). Setting
The number of read cycles is set by the <OPWR1:0> of the PMEMCR register.
The page size (the number of bytes) of ROM in the CPU size is set by the <PR1:0> of
t
Figure 3.6.2 Page mode access Timing (8-byte example)
Note: Set the number of waits (“n”) using the control register (BnCSL) in each block
<OPWR1> <OPWR0>
CYC
<PR1>
t
0
0
1
1
0
0
1
1
AD3
address area.
t
RD3
+0
<OPWR1:0> (PMEMCR register)
<PR1:0> Bit (PMEMCR register)
<PR0>
Data
input
0
1
0
1
0
1
0
1
92CH21-119
t
t
1 state (n-1-1-1 mode) (n ≥ 2)
2 state (n-2-2-2 mode) (n ≥ 3)
3 state (n-3-3-3 mode) (n ≥ 4)
(Reserved)
64 bytes
32 bytes
16 bytes (Default)
8 bytes
HA
AD2
Number of Cycle in a Page
+1
ROM Page Size
Data
input
t
t
HA
AD2
+2
Data
input
t
t
HA
AD2
+3
Data
input
TMP92CH21
2009-06-19
t
t
HA
HR