TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 373

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.14.6
3.14.6.1 Description of Operation
3.14.6.2 Random Access Type
Built-in RAM Type LCD driver Mode
CPU.
instruction is executed the LCDC outputs a chip select signal to the LCD driver
connected externally by the control pin (LCP0...). Therefore control of data
transmission numbers corresponding to LCD size is controlled by CPU instruction.
There are 2 kinds of LCD driver address in this case, which are selected by the
LCDCTL<MMULCD> register.
memory access timing section.
3C0000H to
3D0000H to
3E0000H to
3F0000H to
Address
3CFFFFH
3DFFFFH
3EFFFFH
3FFFFFH
Data transmission to the LCD driver is executed by a transmit instruction from the
After setting operation mode of to the control register, when a CPU transmit
This corresponds to address direct writing type LCD driver when <MMULCD> = “1”.
The transmission address can also assign the memory area 3C0000H − 3FFFFF, the
four areas each being 64 Kbytes.
Interface and access timing are the same as for normal memory. Refer to the
Table 3.14.2 Racdom Access Type Built-in RAM Type LCD driver
Built-in RAM LCDD1
Built-in RAM LCDD2
Built-in RAM LCDD3
Built-in RAM LCDD4
Function
92CH21-371
Chip Enable Terminal
LBCD
LCP0
LLP
LFR
TMP92CH21
2009-06-19