TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 146

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(Value to be compared)
Match with TA0REG
X: Don't care, −: No change
TA01RUN
TA01MOD
TA0REG
TA1FFCR
PCCR
PCFC
TA01RUN
Register buffer
overflow is detected when the TA0REG double buffer is enabled.
Example: To output the following PWM waves on the TA1OUT pin (at f
2
n
To achieve a 51.2-μs PWM cycle by setting φT1 (= (16/fc)s (@f
51.2 μs ÷ (16/fc)s = 128
2
Therefore n should be set to 7.
Since the low level period is 36.0 μs when φT1 = (16/fc)s,
set the following value for TREG0:
TA0REG
In this mode the value of the register buffer will be shifted into TA0REG if 2
Use of the double buffer facilitates the handling of low duty ratio waves.
overflow
n
= 128
36.0 μs ÷ (16/fc)s = 90 = 5AH
MSB
← −
← 1
← 0
← X
← −
← −
← 1
7
6
X
1
1
X
−
−
X
Figure 3.7.18 Register Buffer Operation
5
X
1
0
X
−
−
X
4
X
0
1
X
−
−
X
Up counter = Q
36.0 μs
51.2 μs
3
−
−
1
1
−
−
−
2
−
−
0
0
−
−
1
92CH21-144
1
−
0
1
1
−
−
−
LSB
Q
1
1
0
0
1
0
X
1
1
1
Q
2
Stop TMRA0 and clear it to 0
Select 8-bit PWM mode (cycle: 2
input clock.
Write 5AH.
Clear TA1FF to 0, enable the inversion and double buffer.
Set PC0 as the TA1OUT pin.
Start TMRA0 counting.
C
= 40 MHz):
Shift into TA0REG
Up counter = Q
TA0REG (Register buffer)
write
7
Q
) and select φT1 as the
2
2
C
TMP92CH21
Q
= 40 MHz).
3
2009-06-19
n