TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 351

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

LCDDVM
(0283H)
(Reference) In general, prime numbers (3, 5, 7, 11, 13 ...) are best for the value of the LCDDVM
Bit symbol
Read/Write
Reset State
Function
register.
(3) Divide frame adjust function
Note: Availability of this function depends on the actual LCD driver or LCD panel used.
in large LCD panels.
alternates between high and low level with each LLP cycle for the LCDDVM
register values given below.
alternates between high and low level with each LBCD cycle. This function is not
affected by the LBCD timing.
FMN7
The DIVIDE FRAME function allows for adjustments to reduce uneven display
When this function is enabled by setting <FRMON> = 1, the LFR signal
When this function is disabled by setting <FRMON> = 0, the LFR signal
0
7
We recommend checking that register’s value when used in the proposed
environment.
FMN6
0
6
Divide Frame Register
FMN5
92CH21-349
0
5
Setting DVM bit7 to bit0
FMN4
0
4
R/W
FMN3
0
3
FMN2
0
2
FMN1
0
1
TMP92CH21
2009-06-19
FMN0
0
0