TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 24

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

PLLCR0
(10E8H)
PLLCR1
(10E9H)
PxDR
(xxxxH)
Note: Ensure that the logic of PLLCR0<LUPFG> is different from 900/L1’s DFM.
Bit symbol
Read/Write
Reset state
Function
Bit symbol
Read/Write
Reset state
Function
Bit symbol
Read/Write
Reset state
Function
(Purpose and use)
This register is used to set each pin status at stand-by mode.
All ports have registers of the format shown above. (“x” indicates the port name.)
For each register, refer to “3.5 Function of ports”.
Before “Halt” instruction is executed, set each register according to the expected pin-status. They will be effective
after the CPU has executed the “Halt” instruction.
This is the case regardless of stand-by mode (IDLE2, IDLE1 or STOP).
The output/input buffer control table is shown below.
Control
on/off
0: OFF
1: ON
PLLON
Note 1: OE denotes an output enable signal before stand-by mode.
Note 2: “n” in PxnD denotes the bit number of PORTx.
Px7D
R/W
7
7
7
0
1
OE
0
0
1
1
Basically, PxCR is used as OE.
Select fc
clock
0: f
1: f
PxnD
FCSEL
Px6D
0
1
0
1
OSCH
PLL
R/W
6
6
6
0
1
Figure 3.3.6 SFR for Drive Register
Output Buffer
Figure 3.3.5 SFR for PLL
Lock up
timer
status flag
0: Not end
1: End
Output/input buffer drive-register for stand-by mode
LUPFG
OFF
OFF
OFF
ON
Px5D
R
5
0
5
5
1
92CH21-22
Input Buffer
Px4D
4
4
4
1
OFF
OFF
OFF
ON
R/W
Px3D
3
3
3
1
Px2D
2
2
2
1
Px1D
1
1
1
1
TMP92CH21
2009-06-19
Px0D
0
0
0
1