TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 276

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.10.8
USB Device answer
detecting of hardware reset, detecting of USB bus reset, and enumeration answer.
(1) Bus reset detect condition.
(2) Detail of STATUS register
The USB controller (UDC) sets various registers and initialization in the UDC in
Each condition is explained below.
register, and it prepares enumeration operation from USB host. After detecting a USB
reset, the UDC sets ENDPOINT0 to control transfer type 8-byte payload and default
address for using default pipe. Any endpoint other than this is prohibited.
endpoint in the UDC.
conditions for each transfer type.
the results of various transfers. It can be confirmed previous result that is transferred
to endpoint by confirming from external of UDC.
showed is different for each transfer mode. Therefore, please refer to each transfer
mode column below.
When the UDC detects a bus reset on the USB signal line, it initializes internal
Status register that was prepared for each endpoint shows the condition of each
Each condition affects the various USB transfers. Refer to chapter 5 for the changing
EPx_STATUS register value is 0 to 3, and its conditions are shown below. 0 to 4 are
These conditions mean that the endpoint is operating normally. The meaning that is
Register name
ENDPOINT STATUS
0
1
2
3
4
READY
DATAIN
FULL
TX_ERR
RX_ERR
EP0
Except for EP0
92CH21-274
Initial value
1CH
00H
TMP92CH21
2009-06-19