TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 517

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

LCDCCR0
LCDCCR1
LCDCCR2
LCDRP10
LCDRP32
LCDRP54
LCDRP76
Symbol
LCDSCC
(6) LCD controller (2/6)
red palette
register 10
red palette
register 32
red palette
register 54
red palette
register 76
register 0
register 1
register 2
Name
counter
register
counter
counter
counter
source
clock
clock
clock
LCD
clock
LCD
LCD
LCD
LCD
LCD
LCD
LCD
Address
028AH
0287H
0288H
0289H
0291H
0292H
0293H
0294H
LLPSU7
SCC7
1R3
3R3
5R3
7R3
7
0
0
0
0
1
1
256 color STN mode
256 color STN mode
256 color STN mode
256 color STN mode
LLPSU6
RED1 level setting
RED3 level setting
RED5 level setting
RED7 level setting
SCC6
1R2
3R2
5R2
7R2
6
0
0
0
1
0
1
R/W
R/W
R/W
R/W
TFT source driver, LLP_Enable signal: f
92CH21-515
LLPSU5
SCC5
1R1
3R1
5R1
7R1
LCDC source clock counter bit7 to bit0
5
0
0
1
1
1
1
High width time for LLP signal
Set up time of LCP:
SYSCLK pulse number × 8
Set up time of TFT source driver LLP signal
(Offset time is 14 to 16 SYSCLK)
LLPSU4
TLDE4
SCC4
1R0
3R0
5R0
7R0
4
0
0
0
0
0
0
0
R/W
R/W
LLPSU3
TLDE3
SCC3
0R3
2R3
4R3
6R3
3
0
0
0
0
0
1
1
Pre LCP1 CLK: LCP1 pulse
number
Dummy clock number until valid
clock of gate driver LCP1
256 color STN mode
256 color STN mode
256 color STN mode
256 color STN mode
LLPSU2
PCPV2
TLDE2
RED0 level setting
RED2 level setting
RED4 level setting
RED6 level setting
SCC2
R/W
0R2
2R2
4R2
6R2
SYS
2
0
0
0
0
0
1
0
1
× 8
R/W
R/W
R/W
R/W
LLPSU1
PCPV1
TLDE1
SCC1
R/W
0R1
2R1
4R1
6R1
1
0
0
0
0
0
0
0
0
TMP92CH21
2009-06-19
LLPSU0
PCPV0
TLDE0
SCC0
0R0
2R0
4R0
6R0
0
0
0
0
0
0
0
0
0