TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 410

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

NDCR
(01C0H)
Bits
7:1
0
Note: After writing <RST> register, several waits are required (about 10 states) before accessing the NDFC.
3.17.4.8 NAND-Flash Reset Register (ND0FRSTR and ND1FRSTR)
3.17.4.9 NAND-Flash Control Register (NDCR)
Bit symbol
Read/Write
Reset State
Function
Mnemonic
RST
−
Figure 3.17.9 NAND-Flash Reset Register (ND0FRSTR and ND1FRSTR)
0: Channel 0
1: Channel 1
CHSEL
R/W
Field Name
7
0
Reset
−
6
Reserved
Reset (Default: 0)
By setting this bit, reset the NDFC (except NDCR<CHSEL> register).
By reset, this bit is automatically cleared to “0”.
0: Don’t care
1: Reset
92CH21-408
5
7
6
4
5
Description
4
3
3
2
2
1
1
TMP92CH21
RST
R/W
0
0
2009-06-19
: Type
: Default
0