TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 29

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.3.4
<PLLON>
<FCSEL>
PLL output: f
Lock up timer
<LUPFG>
System clock f
Example 1: PLL starting
PLLCR0
PLLCR1
LUP:
X: Don’t care
Clock Doubler (PLL)
low-speed-frequency oscillator can be used, even though the internal clock is
high-frequency.
before use.
and it is measured by a 16-stage binary counter. Lock up time is about 1.6 ms at f
MHz.
Note 1: Input frequency range for PLL
Note 2: PLLCR0<LUPFG>
PLL outputs the f
A reset initializes PLL to stop status, so setting to PLLCR0, PLLCR1 register is needed
As with an oscillator, this circuit requires time to stabilize. This is called the lock up time
PLL
The input frequency range (High-frequency oscillation) for PLL is as follows:
f
The logic of PLLCR0<LUPFG> is different from 900/L1’s DFM.
Exercise care in determining the end of lock up time.
The following is an example of settings for PLL starting and PLL stopping.
OSCH
SYS
EQU
EQU
BIT
JR
LD
LD
= 6 to 10 MHz (V
(PLLCR1),
(PLLCR0),
10E8H
10E9H
5, (PLLCR0)
Z, LUP
Starts PLL operation and
starts lock up
PLL
1 X X X X X X X B ;
X 1 X X X X X X B ;
clock signal, which is four times as fast as f
CC
92CH21-27
Counts up by
= 3.0 to 3.6 V)
During lock up
f
OSCH
;
;
Detects end of lock up.
Enables PLL operation and starts lock up
Changes fc from 10 MHz to 40 MHz.
Lock up ends
Changes from 10 MHz to 40 MHz
After lock up
TMP92CH21
2009-06-19
OSCH
.
OSCH
= 10
. A