TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 115

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(4) Wait control
MHz).
the write cycle and the read cycle. <BnWW2:0> is set using the same method as
<BnWR2:0>.
(i) Waits number fixed mode
(ii)
The external bus cycle completes a wait of at least two states (100 ns at f
Setting the <BnWW2:0> and <BnWR2:0> of BnCSL specifies the number of waits in
Note 1: For SDRAM, the above setting is ineffective. Refer to 3.16 SDRAM controller.
Note 2: For NAND flash, this setting is ineffective.
<BnWW2>
<BnWR2>
states is selected from 2 states (0 waits) to 6 states (4 waits).
continuously while the signal is active. The bus cycle is a minimum 2 states. The
bus cycle is completed if the wait signal is non active (“High” level) at the second
state. The bus cycle continues if the wait signal is active after 2 states or more.
WAIT
The bus cycle is completed following the number of states set. The number of
This mode samples the
0
0
1
1
1
0
For RAM built-in LCDD, this setting is effective.
pin input mode
<BnWW>/<BnWR> (BnCSL Register)
<BnWW1>
<BnWR1>
Others
0
1
0
1
1
1
92CH21-113
<BnWW0>
<BnWR0>
WAIT
0
1
1
1
0
1
input pins. In this mode, a wait is inserted
2 states (0 waits) access fixed mode
3 states (1 wait) access fixed mode (Default)
4 states (2 waits) access fixed mode
5 states (3 waits) access fixed mode
6 states (4 waits) access fixed mode
(Reserved)
WAIT
pin input mode
Function
TMP92CH21
2009-06-19
SYS
= 20