TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 14

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.
3.1
3.1.1
Operation
This section describes the basic components, functions and operation of the TMP92CH21.
CPU
The TMP92CH21 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU)
CPU Outline
TLCS-900/L1 CPU. The TLCS-900/H1 CPU has an expanded 32-bit internal data bus to
process instructions more quickly.
The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the
The following is an outline of the CPU:
External SRAM, Masked ROM
Internal operating frequency
Width of CPU address bus
Instruction queue buffer
Width of CPU data bus
External NAND flash
Minimum instruction
Minimum bus cycle
Internal boot ROM
External SDRAM
Conditional jump
execution cycle
Instruction set
Parameter
Internal RAM
Internal I/O
CPU mode
Micro DMA
Table 3.1.1 TMP92CH21 Outline
92CH21-12
1-clock access (50 ns at f
8- or 16- or 32-bit 2-clock access
2-clock (100 ns at f
16- or 32-bit min. 1-clock access
1-clock (50 ns at f
8- or 16-bit 5 to 6-clock access
Compatible with TLCS-900/L1
8- or 16-bit 2-clock access or
(LDX instruction is deleted)
8-bit min. 4-clock access
(waits can be inserted)
(waits can be inserted)
32-bit 1-clock access
32-bit 2-clock access
Maximum mode only
TMP92CH21
Max 20 MHz
8 channels
12 bytes
24 bits
32 bits
SYS
SYS
SYS
=20MHz)
=20MHz)
= 20MHz)
TMP92CH21
2009-06-19