TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 539

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

I2SBUFR
Symbol
I2SBUFL
I2SCTL0
(18) I
2
S
buffer (R)
register 0
buffer (L)
I
I
Name
2
2
control
S FIFO
S FIFO
I
2
S
Address
(Prohibit
(Prohibit
080EH
0800H
0808H
080FH
RMW)
RMW)
Transmit
0: Stop
1: Start
WS level
0: Low left
1: High left
I2SWLVL
R15/R7
L15/L7
TXE
R/W
R/W
7
0
0
Mode
0: I
1: SIO
Clock
edge
0: Falling
1: Rising
R14/R6
L14/L6
EDGE
FMT
R/W
R/W
2
S
6
0
0
92CH21-537
Register for transmitting buffer (FIFO)
Register for transmitting buffer (FIFO) (Left channel)
Status
0: Stop
1: Under
Select for
stereo
0: Stereo
(2 channel)
1: Monaural
(1 channel)
I2SFSEL
R13/R5
L13/L5
transmitting
BUSY
R/W
5
R
0
0
First bit
0: MSB
1: LSB
Clock
enable
(After
transmit)
0: Operation
1: Stop
I2SCKE
R12/R4
L12/L4
R/W
R/W
DIR
4
0
0
Undefined
Undefined
W
W
Bit
number
0: 8 bits
1: 16 bits
R11/R3
L11/L3
R/W
BIT
3
0
(Right channel)
Baud rate
00: f
01: f
R10/R2
L10/L2
MCK1
R/W
2
0
SYS
SYS
/2 11: f
10: f
R9/R1
MCK0
L9/L1
R/W
SYS
SYS
1
0
TMP92CH21
/4
/8
2009-06-19
WS clock
0: fs/4
1: TA1OUT
System
clock
0: Disable
1: Enable
SYSCKE
I2SWCK
R8/R0
L8/L0
R/W
R/W
0
0
0