TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 268

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

EPx_DATASET_A
EPx_DATASET_B
EPx_DATASET
EPx_BRD
BRD
SOF
Note: EPx_DATASET changes at 2 clocks of 12MHz after receiving SOF. Read data from FIFO after EPx_DATASET
is rising.
the transaction uses the same flow.
frame is not renewed. There is no problem in receiving PID and if frame data
is received with CRC error, USB sets LOST to STATUS on FRAME register,
and exact frame number is unknown. However, in this case, SOF is asserted
and FIFO condition is renewed. If SOF token is received without transmit and
transfer Isochronous in frame, UDC clears FIFO (X Condition) and sets
STATUS to FULL.
In renewed frame, Packet A’s FIFO interchanges with packet B’s FIFO, and
If SOF token is not received by error and so on, this data is lost because the
These are shown in Figure 3.10.12.
Figure 3.10.11 Isochronous Receiving mode
OUT
DATA0
2clocks (12MHz)
92CH21-266
OUT
DATA0
OUT
DATA0
OUT
DATA0
TMP92CH21
2009-06-19