TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 383

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

3.16 SDRAM Controller (SDRAMC)
CPU/LCDC.
(1) Support SDRAM
(2) Initialize function
(3) Access mode
(4) Access cycle
(5) Refresh cycle auto generate
The TMP92CH21 includes an SDRAM controller which supports SDRAM access by
The features are as follows.
Note 1: Display data for LCDC must be set from the head of each page.
Note 2: Condition of SDRAM’s area set by CS1 or CS2 setting of memory controller.
Auto-refresh is generated while another area is being accessed.
Refresh interval is programmable.
Self-refresh is supported
Data rate type:
Bulk of memory:
Number of banks:
Width of data bus:
Read burst length:
Write mode:
All banks precharge command
8 times auto refresh command
Set the mode register command
Read burst length
Addressing mode
CAS latency (clock)
Write mode
CPU Access (Read/write)
LCDC Burst Access (Read only)
Read cycle:
Write cycle:
Access data width:
Read cycle:
Over head:
Access data width:
Only SDR (Single data rate) type
16/64/128/256/512 Mbits
2/4 banks
16/32
1 word/full page
Single/burst
1 word− 4 states/full page − 1 state
Single − 3 states/burst − 1 state
8 bits/16 bits/32 bits
1 word (50 ns at f
4 states (200 ns at f
16 bits/32 bits
1 word/full page selectable
92CH21-381
Single/burst selectable
CPU Access
Sequential
SYS
SYS
2
= 20 MHz)
= 20 MHz)
LCDC Access
Sequential
Full page
2
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TMP92CH21
2009-06-19