TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 39

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

(3) Operation
Interrupt for
release
Interrupt for
release
D0 to D31
D0 to D31
A0 to A23
A0 to A23
Figure 3.3.8 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt
Figure 3.3.7 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt
1.
2.
WR
WR
RD
RD
X1
X1
IDLE2 mode
IDLE2 setting register, can take place. Instruction execution by the CPU stops.
mode halt state by an interrupt.
IDLE1 mode
operate. The system clock stops.
system clock; however, clearance of the halt state (e.g., restart of operation) is
synchronous with it.
an interrupt.
In IDLE2 mode only specific internal I/O operations, as designated by the
Figure 3.3.7 illustrates an example of the timing for clearance of the IDLE2
In IDLE1 mode, only the internal oscillator and the RTC and MLD continue to
In the halt state, the interrupt request is sampled asynchronously with the
Figure 3.3.8 illustrates the timing for clearance of the IDLE1 mode halt state by
Data
Data
92CH21-37
IDLE1
IDLE2
mode
mode
TMP92CH21
2009-06-19
Data
Data