TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 216

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

EP3_STATUS
EP0_STATUS
EP4_STATUS
EP6_STATUS
EP1_STATUS
EP2_STATUS
EP5_STATUS
EP7_STATUS
(0793H)
(0790H)
(0791H)
(0792H)
(0794H)
(0795H)
(0796H)
(0797H)
TOGGLE Bit (Bit6)
SUSPEND (Bit5)
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
3.10.3.13 EPx_STATUS Register (x: 0 to 7)
0: TOGGLE
1: TOGGLE
0: RESUME
1: SUSPEND
Note: EP4, 5, 6 and 7_STATUS registers are not used in the TMP92CH21.
to all endpoints.
These registers are status registers for each endpoint. The <SUSPEND> is common
7
7
7
7
7
7
7
7
Bit0
Bit1
TOGGLE
TOGGLE
TOGGLE
TOGGLE
TOGGLE
TOGGLE
TOGGLE
TOGGLE
6
R
6
R
6
R
6
R
6
R
6
R
6
R
6
R
0
0
0
0
0
0
0
0
SUSPEND
SUSPEND
SUSPEND
SUSPEND
SUSPEND
SUSPEND
SUSPEND
SUSPEND
92CH21-214
5
R
5
R
5
R
5
R
5
R
5
R
5
R
5
R
This bit shows status of toggle sequence bit.
0
0
0
0
0
0
0
0
This bit shows status of UDC power management.
In the SUSPEND status, access to UDC is limited.
For details, refer to 3.10.9.
STATUS[2]
STATUS[2]
STATUS[2]
STATUS[2]
STATUS[2]
STATUS[2]
STATUS[2]
STATUS[2]
4
R
4
R
4
R
4
R
4
R
4
R
4
R
4
R
1
1
1
1
1
1
1
1
STATUS[1]
STATUS[1]
STATUS[1]
STATUS[1]
STATUS[1]
STATUS[1]
STATUS[1]
STATUS[1]
3
R
3
R
3
R
3
R
3
R
3
R
3
R
3
R
1
1
1
1
1
1
1
1
STATUS[0]
STATUS[0]
STATUS[0]
STATUS[0]
STATUS[0]
STATUS[0]
STATUS[0]
STATUS[0]
R
R
R
R
R
R
R
R
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
FIFO_DISABLE
FIFO_DISABLE
FIFO_DISABLE
FIFO_DISABLE
FIFO_DISABLE
FIFO_DISABLE
FIFO_DISABLE
FIFO_DISABLE
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
0
0
0
0
0
0
0
0
TMP92CH21
2009-06-19
STAGE_ERR
STAGE_ERR
STAGE_ERR
STAGE_ERR
STAGE_ERR
STAGE_ERR
STAGE_ERR
STAGE_ERR
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
0
0
0
0
0
0
0