TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 186

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Protocol
1.
2.
3. The master controller transmits data one frame at a time. Each frame includes an 8-bit
4.
5.
6. The other slave controllers (whose <WU> bits remain at 1) ignore the received data
select code which identifies a slave controller. The MSB (bit8) of the data (<TB8>) is set
to 1.
because their MSBs (bit8 or <RB8>) are set to 0, disabling INTRX0 interrupts.
The slave controller whose <WU> bit = 0 can also transmit to the master controller. In
this way it can signal the master controller that the data transmission from the master
controller has been completed.
Select 9-bit UART mode on the master and slave controllers.
Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving.
Each slave controller receives the above frame. Each controller checks the above select
code against its own select code. The controller whose code matches clears its <WU> bit
to 0.
The master controller transmits data to the specified slave controller (the controller
whose SC0MOD0<WU> bit has been cleared to 0). The MSB (bit8) of the data (<TB8>)
is cleared to 0.
Start
Start
Bit0
Bit0
92CH21-184
1
1
Select code of slave controller
2
2
3
3
Data
4
4
5
5
6
6
7
7
Bit8
“1”
“0”
8
TMP92CH21
Stop
Stop
2009-06-19