TMP92xy21FG Toshiba, TMP92xy21FG Datasheet - Page 182

• Manufacturer Part Number: TMP92xy21FG
• Manufacturer: Toshiba

Specifications of TMP92xy21FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 16
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: 1
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 1
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 82
• Power Supply Voltage(v): 3.0 to 3.6

Note:
Figure 3.9.21 Receiving Operation in I/O Interface Mode (SCLK0 output mode)
Figure 3.9.22 Receiving Operation in I/O Interface Mode (SCLK0 input mode)
SCLK0 output
(<SCLKS> = 1:
falling edge mode)
SCLK0 output
(<SCLKS> = 0:
rising edge mode)
RXD0
IRX0C
(INTRX0 interrupt
request)
2.
The system must be put in the receive-enable state (SC0MOD0<RXE> = 1) before data can be received.
SCLK0 input
(<SCLKS> = 0:
rising edge mode)
SCLK0 input
(<SCLKS> = 1:
falling edge mode)
RXD1
IRX0C
(INTRX0 interrupt request)
Receiving
the data is shifted to receiving buffer 1. This is initiated when the receive
interrupt flag INTES0<IRX0C> is cleared as the received data is read. When 8-bit
data is received, the data is transferred to receiving buffer 2 (SC0BUF) following
the timing shown below and INTES0<IRX0C> is set to 1 again, causing an
INTRX0 interrupt to be generated.
input goes active. The SCLK input goes active when the receive interrupt flag
INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is
received, the data is shifted to receiving buffer 2 (SC0BUF) following the timing
shown below and INTES0<IRX0C> is set to 1 again, causing an INTRX0 interrupt
to be generated.
In SCLK output mode the synchronous clock is output on the SCLK0 pin and
Setting SC0MOD0<RXE> to 1 initiates SCLK0 output.
In SCLK input mode the data is shifted to receiving buffer 1 when the SCLK
92CH21-180
Bit0
Bit0
Bit1
Bit1
Bit5
Bit6
Bit6
Bit7
TMP92CH21
2009-06-19
Bit7